A memory consisting essentially of an orthogonal array of such storage cells is known, for example, from U.S. Pat. No. 4,122,544 to David J. McElroy. The two IGFETs of each cell are formed in semiconductor substrate of p-type conductivity, specifically a silicon chip, provided on its surface with n-doped source and drain areas separated by a channel region. A dielectric layer of thermally grown silicon oxide overlies that surface and spans its channel region as well as an adjacent part of the source area. An inaccessible or "floating" gate of phosphorus-doped polycrystalline silicon is embedded in this oxide layer and overlies part of the channel region while being in turn overlain by an accessible control gate of like material extending over the full width of the oxide layer. This accessible gate serves as a common control electrode for the two series-connected transistors referred to above, i.e. the main transistor whose channel underlies the floating gate and the ancillary transistor essentially located in the gap between the floating gate and the drain area.
A writing operation, designed to store a logical "1" in the main transistor, involves the application of a high positive potential (+25 V) to the drain area and to the control gate. This generates an electric field across the oxide film which underlies the floating gate whereby high-speed electrons traversing the channel are attracted into the floating gate. The resulting negative charge of the floating gate prevents the main transistor from conducting when predetermined lower reading voltages on the order of 5 V are applied to the control gate and the drain area; to cancel the stored "1", the control gate is again biased highly positive while the drain voltage is kept low, thereby enabling the extraction of the electronic charge from the floating gate via the oxide film separating the two gates from each other.
It is also known, e.g. from U.S. Pat. No. 3,825,946, to provide two accessible gates in addition to a floating gate for writing and for cancellation or erasure, respectively.
Experience has shown that the time of application of the gate-biasing potential required for cancellation--i.e. for lowering the conduction threshold of the main transistor to a predetermined level--progressively increases with the number of reprogramming operations, presumably on account of a reduced electron permeability of the oxide layer due to the trapping of electrons therein. To a lesser extent this is also true of the time of application of the gate-biasing potential required for the writing of a cell, i.e. for the raising of its conduction threshold to a predetermined elevated level. This phenomenon of aging limits the number of times a given cell can be reprogrammed before excessive time or voltage requirements render it practically unusable.
Certain measures for increasing the possible number of reprogramming operations in such a memory have been disclosed in commonly owned U.S. applications Ser. No. 168,561 (now U.S. Pat. No. 4,357,685) and 168,562 (now abandoned) filed July 14, 1980 by Vincenzo Daniele et al.